This invention relates to a check method of a temporary storage circuit in an electronic control unit for an automobile using a microcomputer for checking the read operation and the write operation of the temporary storage circuit in the electronic control unit for an automobile.
FIG. 5 is a block diagram to show a summary of the internal configuration of a general microcomputer. In a microcomputer MC used with an electronic control unit for an automobile, as shown in FIG. 5, a CPU (central control unit) 3 reads software programs and various data previously stored in ROM (read-only memory) 1 through a register 2 and executes various logical operations based on the software programs and data. At the time, the information in the ROM 1, various pieces of information given from the outside, or the operation processing result, etc., of the CPU 3 is once stored in a temporary storage circuit (RAM (random access memory)) 4 and the CPU 3 uses the information in the RAM 4 to perform operation processing, whereby the whole processing speed is increased. Therefore, the RAM 4 is indispensable for the CPU 3 to perform operation processing and it is extremely important for the RAM 4 to operate normally.
By the way, generally the RAM 4 is often checked for error at the product shipment. After the product shipment, a part of the RAM 4 may become unable to operate normally for some reason of noise, etc., in which case it may be feared that an anomaly may occur in program processing. Particularly, in electronic devices for an automobile, a malfunction caused by an anomaly of the RAM 4 must be absolutely avoided, thus it is more important than anything else to check that the RAM 4 is normal.
Thus, in fact, when the microcomputer MC is started, it is necessary to check whether or not the RAM 4 operates normally together with operation check of the register 2.
To check the RAM 4, in a related art, predetermined data is once written into all addresses in the RAM 4, next the data at the first address is read and whether or not the data is the same as the original data is checked. Subsequently, the address is incremented in order and a similar check is executed on the whole areas of the RAM 4, whereby a check can be made to ensure that the whole RAM 4 is normal.
Specifically, when the RAM 4 is checked, as shown in FIG. 6, first at step So1, the top address of the RAM 4 is set in a predetermined 16-bit register part in the register 2, which will be hereinafter referred to as HL register. At step So2, a numeric value xe2x80x9c00000000xe2x80x9d (the 8-bit numeric value xe2x80x9c00000000xe2x80x9d will be hereinafter abbreviated to xe2x80x9c00H (hexa)) is stored in a predetermined eight-bit (one-byte) register part, which will be hereinafter referred to as A register, different from the HL register for resetting the A register. Subsequently, at step So3, predetermined specific data (data) is stored in the A register. At step So4, the data in the A register is written into xe2x80x9cHLxe2x80x9d address of the HL register and step So5, the numeric value xe2x80x9c00Hxe2x80x9d is stored in the A register for resetting, then at step So6, the data stored at the xe2x80x9cHLxe2x80x9d address of the HL register is read into the A register.
At step So7, whether or not the current value of the A register is the same as the value of the first xe2x80x9cdataxe2x80x9d is determined. If the current value of the A register is the same as the value of the first xe2x80x9cdata,xe2x80x9d control goes to step So8 and whether or not the address xe2x80x9cHLxe2x80x9d is the end address of the RAM 4 is determined. If the address xe2x80x9cHLxe2x80x9d is not the end address, control goes to step So9 and the xe2x80x9cHLxe2x80x9d address of the HL register is incremented and control returns to step So2 and processing is repeated.
If the value of the A register is not the same as the value of the first xe2x80x9cdataxe2x80x9d at step So7, it is assumed that an error occurs in the RAM 4, and control goes to step So10 and predetermined error handling is executed.
Thus, the processing at step So2 and the later steps is repeated until the address xe2x80x9cHLxe2x80x9d reaches the end address of the RAM 4 and when the address xe2x80x9cHLxe2x80x9d reaches the end address, a transition to the next processing as the microcomputer MC is made (step So11).
In FIG. 5, numeral 5 denotes an input I/F (interface) circuit for inputting an external signal to the CPU 3 and numeral 6 denotes an output I/F (interface) circuit for sending the operation processing result of the CPU 3 to the outside. The above-described xe2x80x9cHLxe2x80x9d means that two eight-bit unit registers of high-order eight bits (H) and the low-order eight bits (L) are used to handle one 16-bit (two-byte) data string.
However, in recent years, the program data has become huge and thus the area of the RAM 4 in the microcomputer MC has also become huge and often it has taken a great deal of processing time in checking the RAM 4. Particularly, if whether or not the value of the A register is the same as the value of the first xe2x80x9cdataxe2x80x9d is determined for every address xe2x80x9cHLxe2x80x9d of the HL register as at step So7 in FIG. 6, it is indispensable that the processing time becomes enormous. Thus, the initialization time is prolonged and the transition to the main program is delayed. Consequently, a delay occurs in the control system and there is a possibility that the machine operation may be hindered.
For example, with the electronic control unit for performing head lamp drive processing, if an instantaneous power interruption or reset occurs with the head lamps on during running, a disadvantage of prolonging the time to again turning on the head lamps or the like occurs if the initial processing takes a long time.
This invention relates to a check method of a storage circuit in an electronic control unit for an automobile using a microcomputer for checking the read operation and the write operation of the storage circuit in the electronic control unit for an automobile.
FIG. 11 is a block diagram to show a summary of the internal configuration of a general microcomputer. In a microcomputer MC used with an electronic control unit for an automobile, as shown in FIG. 11, a CPU (central control unit) 203 reads software programs and various data previously stored in a storage circuit (ROM (read-only memory)) 201 through a register 202 and executes various logical operations based on the software programs and data. At the time, the information in the ROM 201 or the operation processing result, etc., of the CPU 203 is once stored in RAM (random access memory) 204 and the CPU 203 uses the information in the RAM 204 to perform operation processing.
In FIG. 11, numeral 205 denotes an input I/F (interface) circuit for inputting an external signal to the CPU 203 and numeral 206 denotes an output I/F (interface) circuit for sending the operation processing result of the CPU 203 to the outside.
With the electronic control unit for an automobile, the CPU 203 takes charge of drive control of various drive systems and thus operates on a major premise that the CPU 203 does not malfunction to ensure sufficient safety of running the automobile. Therefore, it is indispensable that the software programs, etc., previously stored in the ROM 201 should be read into the CPU 203 unerringly. Thus, when the microcomputer MC is started, it is important to check whether or not the software programs, data, and the like are read unerringly from the ROM 201 as well as to check the register 202 and the RAM 204 for operation.
To check the ROM 201, addition operation is performed on the program data corresponding to each address in order and is repeated to the end of the program, then the last low-order 16-bit (two-byte) data is compared with reference data previously stored in a predetermined area of the ROM 201, whereby the ROM 201 can be checked easily.
FIG. 12 is a flowchart to show the operation after the microcomputer MC is started. First, after the power of the microcomputer MC is turned on or reset is released, initialization is executed at step Sp201. Specifically, at step Sp201, the operation frequency magnification of the CPU 203 (FIG. 11) to an operation clock provided by a predetermined oscillator, ports in the input IF 205 and the output interface 206, enable or disable of interrupt service, and the like are set.
Next, at step Sp202, the RAM 204 in the microcomputer MC is checked and further at step Sp203, the ROM 201 in the microcomputer MC is checked. Then, at steps Sp204 to Sp207, processing concerning various drive systems including room lamp processing, door lock processing, head lamp processing, and buzzer processing is executed repeatedly every predetermined time. Processing at steps Sp201 to Sp203 is generally called initial processing In and processing at steps Sp204 to Sp207 is generally called main processing Mn.
Checking the ROM 201 at step Sp203 in FIG. 12 will be discussed in detail with reference to a flowchart of FIG. 13. When the ROM 201 is checked, first the register 202 is checked at step So201 in FIG. 13, next at step So202, a numeric value of zero is assigned to a 16-bit register part, which will be hereinafter referred to as BC register, into which a predetermined eight-bit register part (B register) and a predetermined eight-bit register part (C register) following the B register are combined for initialization. At step So203, the top address of the ROM 201 is set in a predetermined 16-bit register part, which will be hereinafter referred to as HL register, as a value (address) of xe2x80x9cHL.xe2x80x9d
Subsequently, at step So204, the data at the address xe2x80x9cHLxe2x80x9d of the ROM 201 is read and is written into a predetermined eight-bit register part (A register). At step So205, the value in the A register is added to the value in the BC register and the result is new data in the BC register.
Next, at step So206, the value of the address xe2x80x9cHLxe2x80x9d is incremented and at step So207, the incremented address xe2x80x9cHLxe2x80x9d is compared with the value of subtracting numeric value xe2x80x9ctwo bytesxe2x80x9d from the end address of the ROM 201. If the incremented address xe2x80x9cHLxe2x80x9d is equal to or less than the value of subtracting numeric value xe2x80x9ctwo bytesxe2x80x9d from the end address of the ROM 201, steps So204 to So207 are repeated. On the other hand, if the incremented address xe2x80x9cHLxe2x80x9d is greater than the value of subtracting numeric value xe2x80x9ctwo bytesxe2x80x9d from the end address of the ROM 201, control goes to step So208.
At step So208, the value of subtracting numeric value xe2x80x9cone bytexe2x80x9d from the end address of the ROM 201 is stored in a predetermined 16-bit register part, which will be hereinafter referred to as DE register. A predetermined eight-bit register part (D register) and a predetermined eight-bit register part (E register) following the D register are used in combination as the DE register. The address subtracting numeric value xe2x80x9cone bytexe2x80x9d from the end address of the ROM 201 means the head position of the last eight-bit (one-byte) data in the ROM 201 and here, the above-mentioned reference data is previously stored.
The numeric value xe2x80x9cDExe2x80x9d in the DE register is read as address and step So209, the data stored at the address xe2x80x9cDExe2x80x9d in the ROM 201 (reference data) is read and is stored in the HL register.
At step So210, the value in the HL register (reference data) is compared with the value in the BC register (low-order 16-bit data provided by adding the program data at the addresses) and if they differ, control goes to step So211 and predetermined error handling is performed. On the other hand, if the value in the HL register and the value in the BC register match, it can be determined that all values in the ROM 201 repeatedly added at step So205 have been read normally. In this case, control goes to step So212 and the main processing Mn is executed.
However, in recent years, the program data has become huge and thus the storage area in the ROM 201 has also become large. Therefore, to use the method of adding the data in the address order of the ROM 201 as previously described with reference to FIG. 11, the number of times operation processing is performed becomes enormous. Thus, the initialization time is prolonged and the transition to the main processing Mn at step So212 is delayed. Consequently, a delay occurs in the control system and there is a possibility that the machine operation may be hindered.
For example, with the electronic control unit for performing head lamp drive processing, if an instantaneous power interruption or reset occurs with the head lamps on during running, a disadvantage of prolonging the time to again turning on the head lamps or the like occurs if the initial processing takes a long time.
It is therefore an object of the invention to provide a check method of a temporary storage circuit in an electronic control unit capable of decreasing a delay of a control system by shortening the check processing time of whole RAM and shortening the time taken in initialization processing.
To the end, according to the invention as in aspect 1, there is provided, in an electronic control unit wherein a central control unit once stores various data and a software program in a temporary storage circuit and executes predetermined control processing, a check method of the temporary storage circuit in the electronic control unit for executing an operation check of the temporary storage circuit before the control processing, the check method comprising the first step of predetermined data into the top address of the temporary storage circuit, the second step of reading the data at the top address and writing the data into the next address and the later addresses repeatedly in order, and the third step of comparing the data at the end address with the data at the top address only once after the data is written into the end address at the second step and if the data at the end address and the data at the top address are the same, determining that the read operation and the write operation of the data at all addresses of the temporary storage circuit are normal and on the other hand, if the data at the end address and the data at the top address are not the same, determining that the read operation and the write operation of the temporary storage circuit are abnormal.
In the invention as in aspect 2, the electronic control unit is an electronic control unit for an automobile, installed in an automobile, and the control processing executed by the central control unit of the electronic control unit is drive control of various drive systems of an automobile.
Further, it is therefore another object of the invention to provide a check method of a storage circuit in an electronic control unit capable of decreasing a delay of a control system by shortening the check processing time of whole ROM and shortening the time taken in initialization processing.
To the end, according to the invention as in aspect 3, there is provided, in an electronic control unit wherein a central control unit executes predetermined control processing based on various data and a software program previously stored in a storage circuit, a check method of the storage circuit in the electronic control unit for executing an operation check of the storage circuit, the check method comprising the first step of sensing whether or not the predetermined control processing is in a time wait state after predetermined initial processing, the second step of executing the predetermined control processing if the fact that the predetermined control processing is not in a time wait state is detected at the first step, and the third step of checking the storage circuit within the wait time of the predetermined control processing only if the fact that the predetermined control processing is in a time wait state is detected at the first step.
In the invention as in aspect 4, the third step comprises the steps of sensing whether or not checking the storage circuit is complete and if checking the storage circuit is complete, returning to the first step, incrementing an address of the storage circuit each time the fact that checking the storage circuit is incomplete, each time the address is incremented, accumulating data at the incremented address to provide check sum data, each time the check sum data is provided, sensing whether or not the accumulation processing reaches the last stage based on the incremented address and if the accumulation processing does not reach the last stage, returning to the first step, and if the fact the accumulation processing reaches the last stage is detected, comparing the check sum data with predetermined reference data and if the check sum data and the reference data match, determining that the storage circuit operates normally and on the other hand, if the check sum data and the reference data do not match, determining that the storage circuit is abnormal.
In the invention as in aspect 5, the electronic control unit is an electronic control unit for an automobile, installed in an automobile, and the control processing executed by the central control unit of the electronic control unit is drive control of various drive systems of an automobile.